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| NBXDBA012 3.3 V, 106.25 MHz / 212.5 MHz LVPECL Clock Oscillator The NBXDBA012 dual frequency crystal oscillator (XO) is designed to meet today's requirements for 3.3 V LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 106.25 MHz or 212.5 MHz, ultra low jitter and phase noise LVPECL differential output. This device is a member of ON Semiconductor's PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000. Features http://onsemi.com MARKING DIAGRAM 6 PIN CLCC TBD SUFFIX CASE 848AB DBA012 A WL YY WW DBA012 AWLYYWW * * * * * * * * * LVPECL Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise - 0.4 ps (12 kHz - 20 MHz) Selectable Output Frequency - 106.25 MHz / 212.5 MHz Frequency Stability - 50 PPM Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range 3.3 V 10% This is a Pb-Free Device = NBXDBA012 (50 PPM) = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping Applications NBXDBA012LN1TAG CLCC-6 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. * 1X and 2X Fiber Channel * Host Bus Adapter VDD 6 CLK CLK 54 Crystal PLL Clock Multiplier 1 OE 2 FSEL 3 GND Figure 1. Simplified Logic Diagram (c) Semiconductor Components Industries, LLC, 2007 1 August, 2007 - Rev. 0 Publication Order Number: NBXDBA012/D NBXDBA012 OE 1 6 VDD FSEL 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. 1 2 3 4 5 6 Symbol OE FSEL GND CLK CLK VDD I/O LVTTL/LVCMOS Control Input LVTTL/LVCMOS Control Input Power Supply LVPECL Output LVPECL Output Power Supply Description Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output Frequency Select pin description Table 3. Ground 0 V. Non-Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD - 2 V. Non-Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD - 2 V. Positive power supply voltage. Voltage should not exceed 3.3 V 10%. Table 2. OUTPUT ENABLE TRI-STATE FUNCTION OE Pin Open HIGH Level LOW Level Output Pin Active Active High Z Table 3. OUTPUT FREQUENCY SELECT FSEL Pin Open (pin will float high) HIGH Level LOW Level Output Frequency (MHz) 106.25 106.25 212.5 Table 4. ATTRIBUTES Characteristic ESD Protection Human Body Model Machine Model Value 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VDD Iout TA Tstg Tsol Parameter Positive Power Supply LVPECL Output Current Operating Temperature Range Storage Temperature Range Wave Solder See Figure 6 Condition 1 GND = 0 V Continuous Surge Condition 2 Rating 4.6 25 50 -40 to +85 -55 to +120 260 Units V mA C C C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 NBXDBA012 Table 6. DC CHARACTERISTICS (VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C) Symbol IDD VIH VIL IIH IIL VOH VOL VOUTPP Characteristic Power Supply Current (Note 2) OE and FSEL Input HIGH Voltage OE and FSEL Input LOW Voltage Input HIGH Current Input LOW Current OE FSEL OE FSEL VDD = 3.3 V Output LOW Voltage (Note 2) VDD = 3.3 V Output Voltage Amplitude (Note 2) 2000 GND - 300 -100 -100 -100 -100 VDD-1145 2155 VDD-1945 1355 780 Conditions Min. Typ. 80 Max. 95 VDD 800 +100 +100 +100 +100 VDD-895 2405 VDD-1600 1700 Units mA mV mV mA mA mV mV mV Output HIGH Voltage (Note 2) NOTE: NBX circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. Measurement taken with outputs terminated with 50 ohm to VDD-2 V. Table 7. AC CHARACTERISTICS (VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C) Symbol fCLKOUT Characteristic Output Clock Frequency Conditions FSEL = HIGH FSEL = LOW Df FNOISE Frequency Stability Phase-Noise Performance fCLKout = 106.25 MHz/212.5 MHz 10 Years Aging 100 Hz of Carrier 1 kHz of Carrier 10 kHz of Carrier 100 kHz of Carrier 1 MHz of Carrier 10 MHz of Carrier tjit(F) tjitter RMS Phase Jitter Cycle to Cycle, RMS Cycle to Cycle, Peak-to-Peak Period, RMS Period, Peak-to-Peak tOE/OD tDUTY_CYCLE tR tF tstart Output Enable/Disable Time Output Clock Duty Cycle (Measured at Cross Point) Output Rise Time (20% and 80%) Output Fall Time (80% and 20%) Start-up Time Aging 1st Year 48 50 150 150 1 12 kHz to 20 MHz 1000 Cycles 1000 Cycles 10,000 Cycles 10,000 Cycles -103/-90 -125/-122 -135/-127 -137/-128 -137/-131 -162/-159 0.4 3 15 2 10 0.9 10 35 5 25 200 52 550 550 5 3 1 Min. Typ. 106.25 212.5 50 ppm dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps ps ps ps ps ns % ps ps ms ppm ppm Max. Units MHz Every Year After 1st NOTE: NBX circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. http://onsemi.com 3 NBXDBA012 Table 8. RELIABILITY COMPLIANCE Parameter Shock Mechanical Mechanical Mechanical Mechanical Mechanical Standard Method MIL-STD-833, Method 2002, Condition B MIL-STD-833, Method 2003 AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A Solderability Vibration MIL-STD-833, Method 2007, Condition A MIL-STD-202, Method 215 Solvent Resistance Resistance to Soldering Heat Thermal Shock MIL-STD-203, Method 210, Condition I or J MIL-STD-833, Method 1001, Condition A MIL-STD-833, Method 1004 Environment Environment Moisture Resistance Figure 3. Typical Phase Noise Plot @ 106.25 MHz Figure 4. Typical Phase Noise Plot @ 212.5 MHz Figure 5. Typical Output Waveform @ 106.25 MHz Figure 6. Typical Output Waveform @ 212.5 MHz http://onsemi.com 4 NBXDBA012 NBXDBA012 CLK Driver Device CLK Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device VTT VTT = VDD - 2.0 V Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) Temperature (C) 260 217 temp. 260C 20 - 40 sec. max. peak 3C/sec. max. 6C/sec. max. ramp-up 175 150 cooling pre-heat reflow Time 60180 sec. 60150 sec. Figure 8. Recommended Reflow Soldering Profile http://onsemi.com 5 NBXDBA012 PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB-01 ISSUE O D 4X A B 0.15 C D1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e L R MIN 1.70 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.27 1.37 0.70 REF TERMINAL 1 INDICATOR E2 E1 E 0.08 1.30 6.17 6.66 D2 TOP VIEW A3 0.10 C A A1 SIDE VIEW C D3 e 1 2 3 6X A2 4.37 4.65 1.17 SEATING PLANE SOLDERING FOOTPRINT* 1.50 R E3 0.10 C A B 0.05 C 6X 5.06 6 5 4 6X b BOTTOM VIEW L 2.54 PITCH 6X 1.50 DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 NBXDBA012/D |
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